Hardware Synchronization MCQs: 10 Solved Test-and-Set, Spinlock and Barrier Questions

Atomic instructions turn mutual exclusion into a state trace: identify the old lock value, the write, the winner, and the condition that makes waiters spin. Counter resets and CPU topology then decide whether the same mechanism remains safe across barrier generations or on one versus several cores. Attempt each question before checking its explanation; revise Process Synchronization and Semaphores if the property labels are unfamiliar.

For each trace, separate mutual exclusion, progress, bounded waiting and starvation. Open the linked solved pages after Q1, Q2, Q5, Q9 and Q10; for Q3, Q4 and Q6-Q8, use the Hardware Synchronization learn hub.

1. Interrupt masking and the hardware route to mutual exclusion

Interrupt masking prevents selected interrupt handling; atomic read-modify-write changes state indivisibly. In the simplified single-processor model, disabling interrupts protects a tiny kernel region. Another core still runs.

Q1. Interrupt masking

Previous year question: DSSSB 2021. Practise this question.

Disabling an interrupt is known as ______.

• (a) Masking

• (b) Run

• (c) Stop

• (d) Halt

Answer: (a) Masking.

An interrupt-mask bit controls recognition. Run, Stop, and Halt do not mean interrupt suppression.

Q2. Direct hardware primitive

Previous year question: ISRO 2020. Practise this question.

The hardware implementation which provides mutual exclusion is

• (a) Semaphores

• (b) Test and set instruction

• (c) Both options

• (d) None of the options

Answer: (b) Test and set instruction.

Test-and-set is a CPU atomic primitive. A semaphore is higher-level and relies on atomic support, so (c) blurs the distinction.

Q3. Disable-interrupt mechanism

Consider the following synchronization mechanism and choose the appropriate answer:

• (a) It works on single CPU machines because it disables context switches within the critical region.

• (b) It works on single CPU machines even when there are context switches within the critical region.

• (c) It does not work on single core CPU.

• (d) None of these

Answer: (a).

Suppressing timer preemption prevents another process being dispatched on one CPU. It cannot stop another processor; real kernels keep such regions tiny.

2. Test-and-set: purpose, mutual exclusion, progress and starvation

test-and-set(X) returns old X and atomically writes 1. With X = 0, P1 gets 0 and enters; P2 gets 1 and spins. After release, either may win, without FIFO or bounded waiting.

Q4. Primary purpose of test-and-set

What is the primary purpose of the Test and Set instruction in process synchronization?

• (a) To test whether a process is set to run

• (b) To perform a mathematical calculation

• (c) To provide a mechanism for mutual exclusion

• (d) To evaluate the state of a semaphore

Answer: (c) To provide a mechanism for mutual exclusion.

Its atomic read and write acquire a lock, not schedule or calculate.

Q5. Which critical-section properties actually hold?

Previous year question: GATE 2009. Practise this question.

The enter_CS() and leave_CS() functions to implement critical section of a process are realized using test-and-set instruction as follows:
void enter_CS(X)
{
    while test-and-set(X) ;
}
void leave_CS(X)
{
   X = 0;
}
In the above solution, X is a memory location associated with the CS and is initialized to 0. Now consider the following statements: 
I. The above solution to CS problem is deadlock-free 
II. The solution is starvation free. 
III. The processes enter CS in FIFO order. 
IV More than one process can enter CS at the same time. 
Which of the above statements is TRUE?

• (a) I only

• (b) I and II

• (c) II and III

• (d) IV only

Answer: (a) I only.

The winner makes X: 0 -> 1; losers read 1 and spin, preserving mutual exclusion. Release lets a contender progress, so the model is deadlock-free. No queue means no guaranteed FIFO, bounded waiting, or starvation freedom.

Q6. Mixed-property MSQ

MSQ: select every correct option.

Which of the following is/are true: 

• (a) Kernel is not aware about the behaviour of every user level thread

• (b) User threads can switch faster than Kernel threads

• (c) Test and set lock guarantees progress and mutual exclusion

• (d) User level threads are not suitable for non blocking tasks.

Answer: (a), (b), and (c).

For (a), user-thread management can be kernel-invisible. For (b), switching can avoid the kernel scheduler. For (c), test-and-set gives mutual exclusion and progress, not bounded waiting. Statement (d) is false: user threads suit non-blocking work; a many-to-one model instead risks a blocking call stopping the process.

3. Spinlocks: definition and the single-core versus multi-core trap

Spinning is useful when the expected wait is shorter than blocking and wake-up overhead and the lock holder can run on another core. For ordinary schedulable threads on one core, blocking usually lets the owner run sooner.

Q7. Spinlock definition

What is a spinlock?

• (a) It is a type of semaphore

• (b) It is a type of deadlock

• (c) It is a type of lock which causes a thread trying to acquire it to simply wait in a loop ("spin") while repeatedly checking if the lock is available

• (d) None of the above

Answer: (c).

A spinlock busy-waits; a mutex may put the waiter to sleep.

Q8. Which CPU topology suits spinning?

Which makes more sense when it comes to the critical section problem? 1. “Spin lock with single core cpu” 2. “Spin lock with multi core cpu”

• (a) 1

• (b) 2

• (c) 1&2

• (d) none

Answer: (b) 2.

Multiple cores let the owner run while another spins. On one core, spinning denies the owner CPU time until preemption. Spin only for short, low-contention waits.

4. Worked atomic trace: why the Fetch_And_Add lock fails

Q9. Fetch_And_Add lock

Previous year question: GATE 2012. Practise this question.

Fetch_And_Add(X, i) is an atomic Read-Modify-Write instruction that reads the value of memory location X, increments it by the value i, and returns the old value of X.

Context: It is used in the pseudocode below to implement a busy-wait lock. L is an unsigned integer shared variable initialized to 0. A value of 0 means the lock is available; any non-zero value means it is not available.

• (a) fails as L can overflow

• (b) fails as L can take on a non-zero value when the lock is actually available

• (c) works correctly but may starve some processes

• (d) works correctly without starvation

Answer: (b).

P0 owns the lock at L = 1. P1's Fetch_And_Add(L, 1) returns 1 and makes L: 1 -> 2, entering the loop body. P0 releases, L: 2 -> 0; P1 then writes L = 1. The trace is 1 -> 2 -> 0 -> 1, yet nobody owns the lock. A later process may spin forever.

No overflow is needed. Ownership and L already disagree, before considering starvation.

5. Worked barrier trace: the reset race across two invocations

Q10. Reusable barrier

Previous year question: GATE 2006. Practise this question.

A Barrier is a synchronization construct where a set of processes synchronizes globally. Each process arrives at the barrier and waits for all others to arrive; then all processes leave the barrier.

Given: Number of processes = 3.

• S is a binary semaphore (initialized to 1).

• Shared variables process_arrived and process_left are initialized to 0.

Code:

C
void barrier (void) {
1: P(S);
2: process_arrived++;
3: V(S);
4: while (process_arrived != 3);
5: P(S);
6: process_left++;
7: if (process_left == 3) {
8:     process_arrived = 0;
9:     process_left = 0;
10: }
11: V(S);
}

Q: The above implementation of barrier is incorrect. Which one of the following is true?

• (a) The barrier implementation is wrong due to the use of binary semaphore S.

• (b) The barrier implementation may lead to a deadlock if two barrier invocations are used in immediate succession.

• (c) Lines 6 to 10 need not be inside a critical section.

• (d) The barrier implementation is correct if there are only two processes instead of three.

Answer: (b).

Invocation 1 gives process_arrived: 0 -> 1 -> 2 -> 3, so all pass line 4. A makes process_left: 0 -> 1, returns, then makes process_arrived: 3 -> 4 in invocation 2 and waits. B makes process_left: 1 -> 2; C makes 2 -> 3 and resets both counters, erasing A's arrival. B and C produce only process_arrived: 0 -> 1 -> 2. All wait forever.

The semaphore protects updates. Counter reuse without a generation or two-turnstile design is the defect.

6. Answer-pattern review, score diagnosis and the next practice step

Answer strip: Q1 a, Q2 b, Q3 a, Q4 c, Q5 a, Q6 a+b+c, Q7 c, Q8 b, Q9 b, Q10 b.

• 9 to 10 correct: Redo Q9 and Q10 without notes; write every transition.

• 7 to 8 correct: Redraw both diagrams before reattempting.

• 0 to 6 correct: Rebuild the four critical-section properties, then retry Q1-Q8 before tracing Q9 and Q10.

Q1 to Q3 diagnose vocabulary; Q4 to Q6, test-and-set properties; Q7 to Q8, busy waiting and topology; Q9 to Q10, tracing.

The earlier Operating Systems Process Synchronization MCQs owns the broader survey of Peterson, semaphore ordering and a repair for the GATE 2006 barrier. Q10 here uses that same barrier to trace the exact reset race across two invocations. Continue with GATE Guidance by Sanchit Sir or the GATE CS category. Trace values, review the failed property, then reattempt each miss without its answer.