In the terminology used in the BPSC PGT (Computer Science) Tier-1 2023 paper,…
2023
In the terminology used in the BPSC PGT (Computer Science) Tier-1 2023 paper, in IA-32 architecture, which of the following flags is provided along with the general flags?
Answer: D. More than one of the above — Concept: In IA-32 the 32-bit EFLAGS register is not one homogeneous set of bits. Intel groups its bits by the job they do: the status (condition-code) flags…
- A.
TF
- B.
IOPL
- C.
IF
- D.
More than one of the above
- E.
None of the above
Attempted by 1956 students.
Show answer & explanation
Correct answer: D
Concept: In IA-32 the 32-bit EFLAGS register is not one homogeneous set of bits. Intel groups its bits by the job they do: the status (condition-code) flags record the outcome of the last arithmetic or logical operation, a control flag steers string operations, and a further group of system flags and fields governs the execution environment - debugging, interrupt response and I/O privilege. A question of the form "which flags does the architecture provide alongside the general flags?" is therefore answered by reading off that further group, not by hunting for more result-recording bits.
Group | Bits | Role |
|---|---|---|
Status (condition-code) flags | CF, PF, AF, ZF, SF, OF | record the result of the last arithmetic or logical operation |
Control flag | DF | sets the direction, increment or decrement, for string instructions |
System flags and fields | TF, IF, IOPL, NT, RF, VM, AC, VIF, VIP, ID | govern debugging, interrupt response, I/O privilege and processor mode |
Application: take the three EFLAGS entries named in this item and place each one in that map.
TF, the Trap Flag at bit 8: while it is set the processor raises a debug exception after every instruction, which is exactly how a debugger single-steps through code.
IOPL, the two-bit I/O Privilege Level field at bit positions 12-13, controls the default I/O privilege check rather than imposing an unconditional minimum privilege: CPL numerically no greater than IOPL generally permits IN and OUT, while at CPL greater than IOPL the TSS I/O-permission bitmap can authorize individual ports.
IF, the Interrupt Flag at bit 9: while it is set the processor services maskable hardware interrupts; the STI instruction sets it and CLI clears it.
TF, IF and the IOPL field are all entries in IA-32 EFLAGS beyond the six status flags. The BPSC paper uses “conditional flags” loosely for these additional entries, so its intended classification includes more than one named choice; this is an exam-source convention, not Intel’s strict condition-code taxonomy.
Cross-check and terminology caveat:
Under the strict Intel Software Developer’s Manual naming, TF and IF are system flags and IOPL is a system field; none of the three is a condition-code flag. The condition-code flags are CF, PF, AF, ZF, SF and OF.
In the matching BPSC PGT (Computer Science) Tier-1 2023 paper, the official provisional and final keys use “conditional flags” loosely for the further flags and fields supplied alongside the general status flags and select “More than one of the above.”
Result: for this exact BPSC PYQ, follow the official key: "More than one of the above." That answer reflects the source paper’s loose wording. Under strict Intel terminology, none of TF, IF or IOPL is a condition-code flag: TF and IF are system flags, and IOPL is a system field.