A system bus in which each data item is transferred during a time slice known…
2023
A system bus in which each data item is transferred during a time slice known in advance to both units source and destinations is called :
Answer: D. synchronous bus — Answer: synchronous bus Explanation: A synchronous bus is governed by a shared clock that divides time into fixed slots. Each data transfer occurs during a…
- A.
MIMD
- B.
DMA
- C.
asynchronous bus
- D.
synchronous bus
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Correct answer: D
Answer: synchronous bus
Explanation: A synchronous bus is governed by a shared clock that divides time into fixed slots. Each data transfer occurs during a predetermined time slice (time slot) known to both the sender and receiver, matching the description in the question.
Contrast with an asynchronous bus: transfers are coordinated by handshaking and occur when both ends are ready, so timing is not fixed in predetermined time slices.
Why other terms are incorrect: DMA is a transfer mechanism (Direct Memory Access) and MIMD refers to a parallel processing architecture (Multiple Instruction, Multiple Data); neither describes a bus timing scheme with fixed time slices.