Direct-mapped cache questions become error-prone when bytes, blocks, and lines are mixed. Reduce every address to tag, index, and offset before tracing hits or conflicts. Keep data capacity separate from tag, valid, and dirty-bit overhead.
The core direct-mapping rule
Split every address into tag, index, and offset: offset bits = log2(block size), index bits = log2(cache lines), and the tag takes the remaining address bits. A numeric address: block = floor(address / block size), line = block mod lines. Start with cache memory mapping and hit ratio.
Direct mapping with the modulo rule
Question 1
DSSSB 2018
With respect to cache organisation, direct mapping maps each block of main memory into ________ possible cache line.
A. Only one
B. Two
C. Four
D. Eight
Answer: A. Block b maps to exactly one line, b mod L. Associative caches allow alternatives.
Question 2
ISRO 2011
Consider a direct-mapped cache with 64 blocks and a block size of 16 bytes. To which cache block does byte address 1206 map?
A. does not map
B. 6
C. 11
D. 54
Answer: C. 1206 = 75 × 16 + 6 gives block 75. Line 75 mod 64 = 11; 6 is only the offset.
Direct-mapped cache address fields
See where cache sits in the wider hierarchy for context.
Question 3
GATE 2025, Set 2
For a direct-mapped cache, 4 bits are used for the tag field and 12 bits are used to index into a cache block. The size of each cache block is one byte. Assume that there is no other information stored for each cache block.
Which ONE of the following is the CORRECT option for the sizes of the main memory and the cache memory in this system (byte addressable), respectively?
A. 64 KB and 4 KB
B. 128 KB and 16 KB
C. 64 KB and 8 KB
D. 128 KB and 6 KB
Answer: A. One-byte blocks need no offset bits, so addresses have 4 + 12 = 16 bits: 64 KB. The 2^12 one-byte lines give a 4 KB cache.
Question 4
GATE 2005
Consider a direct-mapped cache of size 32 KB with a block size of 32 bytes. The CPU generates 32-bit addresses. The numbers of cache-index bits and tag bits are, respectively:
A. 10, 17
B. 10, 22
C. 15, 17
D. 5, 17
Answer: A. A 32-byte block needs 5 offset bits; 32 KB / 32 B = 2^10 lines need 10 index bits. Tag: 32 - 10 - 5 = 17.
Question 5
GATE 2017, Set 2
Consider a machine with a byte addressable main memory of 2^32 bytes divided into blocks of size 32 bytes. Assume that a direct mapped cache having 512 cache lines is used with this machine. The size of the tag field in bits is _______
Answer: 18 bits. A 32-byte block gives 5 offset bits; 512 lines give 9 index bits. Tag = 32 - 5 - 9 = 18.
Direct mapping with hexadecimal addresses
Question 6
GATE 2015, Set 3
Consider a machine with a byte addressable main memory of 2^20 bytes, block size of 16 bytes and a direct mapped cache having 2^12 cache lines. Let the addresses of two consecutive bytes in main memory be (E201F)16 and (E2020)16. What are the tag and cache line address (in hex) for main memory address (E201F)16?
A. E, 201
B. F, 201
C. E, E20
D. 2, 01F
Answer: A. A 16-byte block makes the last digit F the offset; 2^12 lines take the next three digits, 201, as index. Tag: E.
Direct-mapped cache tag-store overhead
Question 7
GATE 2011
An 8KB direct-mapped write-back cache is organized as multiple blocks, each size of 32-bytes. The processor generates 32-bit addresses. The cache controller contains the tag information for each cache block comprising of the following.
1 valid bit
1 modified bit
As many bits as the minimum needed to identify the memory block mapped in the cache.
What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?
A. 4864 bits
B. 6144 bits
C. 6656 bits
D. 5376 bits
Answer: D. 8 KB / 32 B = 256 lines mean 8 index and 5 offset bits, so each tag is 32 - 8 - 5 = 19 bits. Adding valid and modified bits: 256 × 21 = 5376.
Question 8
GATE 2025, Set 1
Consider a memory system with 1M bytes of main memory and 16K bytes of cache memory. Assume that the processor generates 20-bit memory address, and the cache block size is 16 bytes. If the cache uses direct mapping, how many bits will be required to store all the tag values? [Assume memory is byte addressable, 1K=2¹⁰, 1M=2²⁰]
A. 6 × 2¹⁰
B. 8 × 2¹⁰
C. 2¹²
D. 2¹⁴
Answer: A. 2^14 / 2^4 = 2^10 lines mean 10 index and 4 offset bits, leaving 20 - 10 - 4 = 6 tag bits. All 2^10 tags take 6 × 2^10 bits.
Direct-mapped conflict misses and locality traces
Question 9
GATE 2006
A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a two dimensional array of size 512×512 with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2. P1:
for (i=0; i<512; i++) {
for (j=0; j<512; j++) {
x += A[i][j];
}
}P2:
for (i=0; i<512; i++) {
for (j=0; j<512; j++) {
x += A[j][i];
}
}P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2 . The value of the ratio M1/M2 is:
A. 0
B. 1/16
C. 1/8
D. 16
Answer: B. Each 128-byte block holds 16 elements, so P1 misses once per block: 262144 / 16 = 16384. P2's 4096-byte column stride spans 32 blocks, cycling 8 of 256 lines and evicting every block before reuse, so all 262144 accesses miss. M1/M2 = 16384/262144 = 1/16.
Question 10
GATE 2022
Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS…). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?
A. Every access to S is a hit.
B. Once P is brought to the cache it is never evicted.
C. At the end of the execution only R and S reside in the cache.
D. Every access to R evicts Q from the cache.
Answer: A, B, and D. P and S occupy the same 64-byte memory block 649, which maps to line 9 with tag 20. P loads that block and S hits it; no Q or R access maps to line 9, so P's block remains resident. Q (tag 24) and R (tag 25) both map to line 10 and evict one another. Thus C is false because P and S remain together in line 9 at the end.
Question 11
GATE 2026, Set 2
Consider a system with a processor and a 4 KB direct mapped cache with block size of 16 bytes. The system has a 16 MB physical memory. Four words P, Q, R, and S are accessed by the processor in the same order 10 times. That is, there are a total of 40 memory references in the sequence P, Q, R, S, P, Q, R, S,…
Assume that the cache memory is initially empty. The physical addresses of the words are given below (1 word = 1 byte).
P: 0x845B32, Q: 0x845B26, R: 0x845B36, S: 0x846B32
Which of the following statements is/are true?
Note: 1K=2¹⁰ and 1M=2²⁰
A. Every access to P results in a cache miss
B. Every access to R results in a cache hit
C. Every access to Q results in a cache miss
D. Except the first access to S, all subsequent accesses to S result in cache hits
Answer: A and B. 16-byte blocks and 256 lines make the last nibble the offset, the next two the index: P 845|B3|2, Q 845|B2|6, R 845|B3|6, S 846|B3|2. Each cycle P misses, reloading tag 845 into B3; R hits that block; S evicts it with tag 846. Q keeps B2, missing only once; S always misses.
Practise timed cache traces with the GATE Test Series.
Reverse direct-mapping calculations
Question 12
GATE 2026, Set 2
Consider a system with 1 MB physical memory and a word length of 1 byte. The system uses a direct mapped cache, with block numbers starting from 0. The word with physical address 0xA2C28 is mapped to the cache block number 176₁₀. The maximum possible size of the cache (in KB) for this configuration is ___________. (answer in integer) Note: 1K=2¹⁰ and 1M=2²⁰
Answer: 128 KB. The eight-bit value 176 = 10110000 appears at address bits 13 through 6 of 0xA2C28, fixing a six-bit offset. The next three higher bits are 0, so index widths from 8 through 11 still select line 176; the following bit is 1, so a 12-bit index would not. The largest valid cache therefore has 2^11 lines of 2^6 bytes each: 2^17 B = 128 KB.
Direct mapping checklist
Run this checklist on every direct-mapping problem:
Convert every size to a power of two first.
offset = log2(block size),index = log2(lines), tag = the rest.Metadata bits are tag + valid + dirty, never data capacity.
A hit needs the index AND the stored tag to match.
Use modulo mapping for line numbers, split address fields from the least significant bit upward, trace conflicting tags one access at a time, and test every allowable index width in reverse problems. Then continue with the full GATE CS learning sequence or browse the wider GATE preparation catalogue.
