DMA questions can look like simple definitions, but one phrase about bus ownership, burst transfer, cycle stealing, or units can change the answer. A reliable method is to identify who owns the bus, keep every rate unit visible, and separate CPU busy time from device transfer time. Attempt each question before reading the answer, then use the explanation to check your reasoning rather than just copying the option.
1. Direct Memory Access basics and the controller's job
The CPU gives the DMA controller the starting address, transfer count, and direction. The controller then requests the bus, moves data directly between the peripheral and main memory, and reports completion. "Without CPU involvement" means that the CPU does not copy every byte. It still handles setup and completion.
Question 1
What role does the DMA controller play in the process of data transfer between peripheral devices and main memory?
A. It bypasses the CPU and transfers data directly between memory and devices.
B. It uses the CPU's ALU for performing all transfers.
C. It interrupts the CPU to process each byte individually.
D. It sends data to the CPU first before writing to memory.
Answer: A. The CPU configures the operation, but the DMA controller becomes bus master for the actual data movement. It normally interrupts the CPU after completion, not once per byte.
Question 2
The interface(s) that provide(s) I/O transfer of data directly to and from the memory unit peripheral is / are termed as : (A) DMA (Direct Memory Access) (B) IOP (Input-Output Processor) (C) Serial Interface (D) Parallel Interface Choose the correct answer from the options given below :
A. (A) Only
B. (B) Only
C. (A) and (B) Only
D. (C) and (D) Only
Answer: C. DMA and an IOP can control direct I/O transfers involving memory. Serial and parallel describe how bits are organised during transfer, not an autonomous memory-transfer controller.
2. HOLD, HLDA and bus handover
The handshake is request, grant, and transfer. The DMA controller requests the system bus. The CPU finishes its current bus cycle and grants control. Only then may the controller drive the address, data, and control lines. In 8085 terminology, these first two signals are HOLD and HLDA.
Question 3
Two control signals in microprocessor which are related to Direct Memory Access (DMA) are
A. INTR & INTA
B. RD & WR
C. S0 & S1
D. HOLD & HLDA
Answer: D. HOLD requests control of the buses, and HLDA acknowledges that the processor has handed them over. INTR and INTA belong to interrupt request and acknowledgement, so they do not form the DMA bus-handover pair.
3. Burst transfer, cycle stealing and bandwidth
Burst mode keeps the bus for a complete block, which favours transfer throughput. Cycle stealing takes one bus cycle at a time and briefly delays the CPU. Transparent DMA waits for bus slots that the CPU is not using. The right mode depends on the objective.
Question 4
In DMA transfer scheme, the transfer scheme other than burst mode is
A. cycle technique
B. stealing technique
C. cycle stealing technique
D. cycle bypass technique
Answer: C. Cycle stealing transfers a word or small unit in an individual bus cycle, then lets the CPU use the bus again.
Question 5
In Direct Memory Access (DMA) _____, a block sequence consisting of a number of memory words is transferred in a continuous burst.
A. Bus granting
B. Burst transfer
C. Cycle stealing
D. Controller count
Answer: B. "Continuous burst" is the decisive clue. Burst transfer keeps bus ownership across the block, whereas cycle stealing returns access between stolen cycles.
Question 6
Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width?
A. Transparent DMA and Polling interrupts
B. Cycle-stealing and Vectored interrupts
C. Block transfer and Vectored interrupts
D. Block transfer and Polling interrupts
Answer: C. Block transfer avoids repeated bus-arbitration overhead, while a vectored interrupt takes the CPU directly to the relevant service routine. This combination targets the highest I/O bandwidth, though a block transfer can pause the CPU longer.
4. Put the complete DMA transfer in order
Use four checkpoints: request, grant, transfer, completion. A controller cannot drive a DMA transfer before the CPU grants bus ownership, and it signals completion after finishing the programmed count.
Question 7
Arrange the given steps required for a Direct Memory Access (DMA) transfer in the correct order. (A) Initiate DMA transfer request (B) Transfer data directly between peripheral and memory (C) Processor grants DMA control over the system bus (D) DMA controller completes data transfer and signals completion Choose the correct answer from the options given below:
A. (C), (A), (B), (D)
B. (A), (C), (B), (D)
C. (A), (B), (C), (D)
D. (C), (B), (A), (D)
Answer: B, which means A -> C -> B -> D. The request must exist before the grant. The grant must occur before direct data movement. Completion can be signalled only after the programmed transfer finishes.
5. Cycle-stealing numericals: convert the rate before choosing
Keep the units on every line. A common chain is processor cycles per second, fraction stolen, DMA cycles per second, bytes per second, and bits per second. If the device rate starts in bits per second, first convert it to characters or bytes.
Question 8
A processor is fetching instructions at the rate of 1 MIPS. A DMA module is used to transfer characters to RAM from a device transmitting at 9600 bps. How much time will the processor be slowed down due to DMA activity?
A. 9.6 ms
B. 4.8 ms
C. 2.4 ms
D. 1.2 ms
Answer: D. Taking 8 bits per character:
9600 bits/s / 8 bits/character = 1200 characters/s.At one stolen cycle per character, DMA steals
1200 cycles/s.The processor provides
1,000,000 cycles/s, so the lost fraction is1200 / 1,000,000 = 0.0012.Over one second, that is
0.0012 s = 1.2 msof slowdown.
Question 9
Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?
A. 2,56,000
B. 3,200
C. 25,60,000
D. 32,000
Answer: C. Work from cycles to the requested unit:
4 MHz = 4,000,000 processor cycles/s.4,000,000 x 0.01 = 40,000 DMA cycles/s.40,000 cycles/s x 8 bytes/cycle = 320,000 bytes/s.320,000 bytes/s x 8 bits/byte = 2,560,000 bits/s.
The option writes this in Indian grouping as 25,60,000. Stopping at bytes per second or applying 1% twice gives a wrong option.
6. DMA setup and completion overhead
Separate device transfer time from CPU busy time. The device may transfer for milliseconds while the CPU spends only a few cycles on setup and completion. Calculate CPU busy time / elapsed transfer time x 100, not the duration of the DMA operation as if the CPU were busy throughout.
Question 10
A hard disk with a transfer rate of 10 Mbytes/ second is constantly transferring data to memory using DMA. The processor runs at 600 MHz, and takes 300 and 900 clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is 20 Kbytes, what is the percentage of processor time consumed for the transfer operation ?
A. 5.0%
B. 1.0%
C. 0.5%
D. 0.1%
Answer: D. Calculate the two times separately:
Transfer time:
20 KB / 10 MB/s = 0.002 s = 2 ms.CPU overhead cycles:
300 + 900 = 1200 cycles.CPU busy time:
1200 / 600,000,000 = 0.000002 s = 2 microseconds.CPU percentage:
(2 microseconds / 2 milliseconds) x 100 = 0.1%.
Using binary interpretations of KB and MB still leads to the listed choice.
7. DMA traps, scorecard and next practice step
Score one point for each correct answer. If you missed Questions 1 to 3, revise controller setup, direct transfer, and HOLD/HLDA. If you missed Questions 4 to 7, revise arbitration, bus ownership, and transfer modes. If you missed Questions 8 to 10, practise unit conversion and separate CPU overhead from elapsed device time.
Before moving on, check that you can:
distinguish CPU setup from DMA data movement;
place request before grant;
identify HOLD and HLDA;
distinguish burst transfer from cycle stealing; and
continue a bytes-per-second result to bits per second when asked.
For a wider Computer Organization sequence, continue with GATE Guidance by Sanchit Sir. If you are ready for timed mixed practice, use the GATE Test Series: Mocks & Topic-wise Tests. You can revise the closest representation topic through Floating Point Representation: IEEE 754 Format. Use DMA, Interrupts and Programmed I/O for GATE: Solved Numericals as the theory entry point for the whole set, especially the rate and overhead methods behind Questions 8 to 10. The GATE CS Exam Preparation Courses & Test Series category is the broader hub.
Now redo Questions 8 to 10 without looking at the calculations, and write request -> grant -> transfer -> completion from memory.
