Performance & Speedup MCQs: 12 Solved Pipelining Questions

Pipeline performance numericals are usually lost because latency, throughput, clock period, CPI and efficiency get mixed into one formula, not because the arithmetic is difficult. Choose an option and write one line of working before revealing each answer. KnowledgeGate has over 70 practice questions on Performance & Speedup, and the GATE CS Exam Preparation page places this practice inside the wider subject route. Questions 8, 9 and 11 are unattributed practice items rather than dated papers, so use the linked Performance & Speedup PYQ Questions hub if you want more questions of that type.

Start with Pipelining Basics MCQs: 10 Solved Questions with Explanations for clock-period, fill-and-drain, interlock and operation-order fundamentals. This set concentrates on performance ratios, saved time, CPI, MIPS, bubbles, efficiency and bottleneck splitting.

Performance and speedup formulas to use before the MCQs

Use these formulas under their stated ideal assumptions:

Take 20 instructions, stage delays of 4, 5, 6, 5, 4 ns, and a 1 ns latch delay. The period is 6 + 1 = 7 ns, so pipelined time is (20 + 5 - 1) x 7 = 168 ns. Non-pipelined time is 20 x (4 + 5 + 6 + 5 + 4) = 480 ns. Speedup is 480 / 168 = 2.857; efficiency is 2.857 / 5 = 0.5714, or 57.14%.

Five stages set only a theoretical ceiling. The slowest stage, latch overhead, fill and drain time, and stalls determine achieved speedup.

Performance and speedup MCQs 1-3: latency, saved time and latch overhead

Question 1

GATE 2000

Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-pipelined but otherwise identical CPU, we can say that:

• A. T1 <= T2

• B. T1 >= T2

• C. T1 < T2

• D. T1 is T2 plus the time taken for one instruction fetch cycle

Answer: B. T1 >= T2.

One instruction still crosses every stage, with possible register overhead. Pipelining improves throughput after instructions overlap, not single-instruction latency.

Question 2

GATE 2005, Information Technology

We have two designs D1 and D2 for a synchronous pipeline processor. D1 has 5 pipeline stages with execution times of 3 nsec, 2 nsec, 4 nsec, 2 nsec and 3 nsec while the design D2 has 8 pipeline stages each with 2 nsec execution time How much time can be saved using design D2 over design D1 for executing 100 instructions?

• A. 214 nsec

• B. 202 nsec

• C. 86 nsec

• D. - 200 nsec

Answer: B. 202 nsec.

D1 takes (100 + 5 - 1) x 4 = 416 nsec; D2 takes (100 + 8 - 1) x 2 = 214 nsec. The saving is 416 - 214 = 202 nsec.

Question 3

GATE 2008, Information Technology

A non pipelined single cycle processor operating at 100 MHz is converted into a synchronous pipelined processor with five stages requiring 2.5 nsec, 1.5 nsec, 2 nsec, 1.5 nsec and 2.5 nsec, respectively. The delay of the latches is 0.5 nsec. The speedup of the pipeline processor for a large number of instructions is

• A. 4.5

• B. 4.0

• C. 3.33

• D. 3.0

Answer: C. 3.33.

The periods are 1 / 100 MHz = 10 nsec and 2.5 + 0.5 = 3 nsec. For a large stream, speedup approaches 10 / 3 = 3.33, not five.

Performance and speedup MCQs 4-6: bottlenecks, clock rates and bubbles

Question 4

GATE 2007, Information Technology

A processor takes 12 cycles to complete an instruction I. The corresponding pipelined processor uses 6 stages with the execution times of 3, 2, 5, 4, 6 and 2 cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed?

• A. 1.83

• B. 2

• C. 3

• D. 6

Answer: B. 2.

The 6-cycle bottleneck clocks the pipeline. Asymptotic speedup is 12 / 6 = 2, while six stages only set the ceiling.

Question 5

ISRO 2016

Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is

• A. 3.2

• B. 3.0

• C. 2.2

• D. 2.0

Answer: A. 3.2.

Times per instruction are 4 / 2.5 GHz = 1.6 ns and 1 / 2 GHz = 0.5 ns. Their ratio gives speedup 1.6 / 0.5 = 3.2.

Question 6

ISRO 2020

Consider a 5-segment pipeline with a clock cycle time 20 ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute 100 instructions. (If an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline.).

• A. 5

• B. 4.03

• C. 4.81

• D. 4.17

Answer: B. 4.03.

Non-pipelined execution needs 100 x 5 = 500 cycles. Pipelining needs 104 + 20 = 124 cycles, so speedup is 500 / 124 = 4.032, approximately 4.03.

Performance and speedup MCQs 7-9: efficiency and MIPS

Question 7

ISRO 2013

A pipeline P operating at 400 MHz has a speedup factor of 6 and operating at 70% efficiency. How many stages are there in the pipeline?

• A. 5

• B. 6

• C. 8

• D. 9

Answer: D. 9.

From E = S / k, k = 6 / 0.70 = 8.57. With integral stages and rounded efficiency, choose 9; 400 MHz is irrelevant.

Question 8

Consider the two processors P1 and P2. MIPS ( Million instruction per second) of P1 is 100 and P2 is 200. Which of the following options are correct?

• A. P1 is better processor than P2

• B. P2 is better processor than P1

• C. both have same capability

• D. none of the above

Answer: D. none of the above.

MIPS is comparable only for equivalent instruction streams under compatible instruction-set and compiler assumptions. The question gives no equivalent workload, so A, B and C do not follow.

Question 9

A non pipeline processor X has a clock rate of 25 MHz. and an average CPI of 4. Processor Y is designed with 5 stages of linear pipeline.However due to latch delay and clock skew effect,the clock rate of Y is only 20 MHz. Which of the following is/are true when finding MIPS rate of non pipeline and pipeline processor during the execution of a particular program.

• A. MIPS rate of Y=20

• B. MIPS rate of X =6.25

• C. MIPS rate of Y = 6.25

• D. none of the above

Answer: A and B.

For X, MIPS = 25 MHz / 4 = 6.25. For Y, CPI approaches 1 and MIPS = 20 MHz / 1 = 20, making A and B true.

Performance and speedup MCQs 10-12: stage splitting, branch CPI and pipeline storage

Question 10

Infosys 2024

Suppose we have 6 pipeline stages naming S1, S2, S3, S4, S5, S6 with stage latencies as 110, 340, 400, 380, 420, 410 nanoseconds respectively. Every pipeline stage have a buffer latency of 10 nanoseconds buffer latency. If one of the pipeline stages is split into 2 equal halves to increase the throughput. Which one of the following stages has to be split to increase the throughput?

• A. S1

• B. S3

• C. S5

• D. S6

Answer: C. S5.

S5 sets the period at 420 + 10 = 430 ns. Splitting it into two 210 ns stages makes S6 the bottleneck, giving 410 + 10 = 420 ns.

Question 11

A Pipeline system overlaps all kind of instructions except branch instructions. Each branch instruction introduces 3 stall cycles. If 20% branch instructions exist here, what will be the updated CPI?

• A. 1.8

• B. 1.6

• C. 2.4

• D. 2.2

Answer: B. 1.6.

Branch penalty averages 0.20 x 3 = 0.60 cycles per instruction. Adding ideal CPI 1 gives 1 + 0.60 = 1.60.

Question 12

ISRO 2023

An instruction pipeline can be implemented by means of

• A. LIFO buffer

• B. FIFO buffer

• C. Stack

• D. None of the above

Answer: B. FIFO buffer.

FIFO preserves the arrival order between pipeline stages. A stack or LIFO buffer sends the newest item first and reverses that order.

Performance and speedup traps

For a timed solve, underline the quantity and unit. Decide whether n is finite or asymptotically large, compute clock period before total time, then check the plausible stage ceiling.

Use Pipelining in Computer Architecture Explained for the full concept sequence. Next, Cache Memory: Mapping and Hit Ratio is the related COA performance numerical, not another pipeline lesson.

Performance and speedup: the next practice step

Redo Questions 2, 5, 6, 9 and 10 without looking. Together they test finite total time, a changed clock frequency, bubbles, MIPS and bottleneck splitting; if one answer fails, return to the formula table and write the unit at every intermediate step. Then attempt them in a different order.

For a sequenced Computer Architecture route that places pipelining beside the rest of COA, use GATE Guidance by Sanchit Sir. The short version is this: speedup is always a ratio of comparable execution times, so never substitute the stage count until balance, overhead, finite fill cost and stalls have all been checked carefully.