Input Output Organisation MCQs: 12 Cross-Concept COA Questions Solved

Input Output Organisation becomes difficult when one option mixes the device's role with the CPU's role. Classify the decisive cue first: storage or spooling, address space, interrupt priority, DMA ownership, or bus bandwidth. Then eliminate options that assign notification, transfer, and arbitration to the wrong component. For the wider Computer Architecture learning path, use GATE Guidance by Sanchit Sir.

Input Output Organisation MCQs: sort the cue before solving

Bucket each question as storage/device, address space/instruction, interrupt/priority, DMA/bus ownership, or bandwidth arithmetic.

The Input Output Organisation cross-concept practice hub adds further mixed questions after you finish the set.

Storage hierarchy and spooling MCQs

Separate storage properties from spooling, which queues shared-device work. File Systems and Disk Scheduling in OS explains the disk bridge.

Q1. Primary storage versus secondary storage

Source: UGC NET 2023

In comparison to secondary computer storage, primary storage is :

• (A) Slower, more expensive per unit of storage and persistent

• (B) Faster, less expensive per unit of storage and persistent

• (C) Faster more expensive per unit of storage and not persistent

• (D) Faster, less expensive per unit of storage and not persistent

Answer: (C) Faster more expensive per unit of storage and not persistent. Here primary storage means main-memory RAM: faster, costlier per unit and volatile. This option-based comparison does not cover every component sometimes called primary storage.

Q2. A spooled output device

Which of the following is an example of a spooled device?

• (A) The terminal used to enter the input data for the C program being executed.

• (B) An output device used to print the output of a number of jobs.

• (C) The secondary memory device in a virtual storage system.

• (D) The swapping area on a disk used by the sapper.

Answer: (B) An output device used to print the output of a number of jobs. Spooling queues jobs on disk for one printer. Virtual-memory backing and swapping solve memory-management problems instead.

I/O instructions and address-space choices

I/O instructions communicate with peripherals through memory space or a separate I/O space. Memory-mapped I/O shares the memory address space and instruction forms; isolated I/O preserves a separate port space.

Q3. Purpose of I/O instructions

Source: NIACL AO IT Specialist 2025

In a typical instruction set architecture, what is the primary purpose of input/output (I/O) instructions?

• (A) To allocate memory for variables during program execution.

• (B) To manage communication between the processor and peripheral devices.

• (C) To directly execute arithmetic operations on memory addresses.

• (D) To switch between different instruction formats dynamically.

Answer: (B) To manage communication between the processor and peripheral devices. They exchange data, control and status information with device interfaces. Allocation, arithmetic and ISA-format design use other mechanisms.

Q4. Isolated I/O, memory-mapped I/O and serial timing

Source: UGC NET 2017

Which of the following is correct statement ?

• (A) In memory - mapped I/O, the CPU can manipulate I/O data residing in interface registers that are not used to manipulate memory words.

• (B) The isolated I/O method isolates memory and I/O addresses so that memory address range is not affected by interface address assignment.

• (C) In asynchronous serial transfer of data the two units share a common clock.

• (D) In synchronous serial transmission of data the two units have different clocks.

Answer: (B) The isolated I/O method isolates memory and I/O addresses so that memory address range is not affected by interface address assignment. Its separate port space preserves memory addresses. Asynchronous transfer lacks a continuous shared clock, while synchronous transfer uses shared or recovered timing, reversing (C) and (D).

Interrupt notification, vectoring and priority MCQs

Separate service notification, ISR identification and request priority. Polling checks repeatedly, while a vectored interrupt supplies identifying information.

Q5. Hardware notification to the CPU

Source: NIACL AO IT Specialist 2018

Hardware mechanism that enables a device to notify the CPU is called:

• (A) busy-waiting

• (B) interrupt

• (C) polling

• (D) DMA

Answer: (B) interrupt. An interrupt signals that a device needs CPU attention. Busy-waiting and polling are CPU checks, while DMA is a transfer mechanism.

Q6. Daisy chaining, vectored interrupts, polling and DMA

Consider the following statements.

I. Daisy chaining is used to assign priorities in attending interrupts.

II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt.

III. In polling,the CPU periodically checks the status bits to know if any device needs its attention.

IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.

Which of the above statements is/are TRUE ?

• (A) I and II only

• (B) I and IV only

• (C) I and III only

• (D) III only

Answer: (C) I and III only. Daisy chaining sets priority and polling checks status, so I and III are true. Vectoring avoids source polling, and arbitration allows one master, so II and IV are false.

DMA and bulk-transfer MCQs

DMA transfers device-memory blocks after setup. Cycle stealing takes individual bus cycles, while burst mode holds the bus for a block.

Q7. Why DMA transfer is advantageous

Source: NIACL AO IT Specialist 2025

DMA transfers are advantageous because they:

• (A) Bypass the CPU during data transfer

• (B) Increase the CPU clock rate

• (C) Reduce memory size

• (D) Eliminate cache misses

Answer: (A) Bypass the CPU during data transfer. The CPU sets up DMA, then the controller copies the block. DMA changes neither clock rate, memory size nor cache behaviour.

Q8. Highest-throughput hard-disk transfer

Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?

• (A) DMA based I/O transfer

• (B) Interrupt driven I/O transfer

• (C) Polling based I/O transfer

• (D) Programmed I/O transfer

Answer: (A) DMA based I/O transfer. DMA moves the block between controller and memory after CPU setup. The other methods need more CPU mediation, reducing bulk throughput.

Q9. DMA modes and CPU utilisation

Which one of the following statements is FALSE?

• (A) In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle

• (B) For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode

• (C) Programmed I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism

• (D) The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts

Answer: (C) Programmed I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism. It is false because programmed I/O occupies the CPU between services. The others correctly describe a stolen word, a higher-throughput burst and faster vector-based ISR location.

Bus ownership and bandwidth calculation MCQs

A grant names the bus owner. For bandwidth, convert width to bytes and divide by total transfer time.

Q10. Role of a Bus Grant signal

Source: NIACL AO IT Specialist 2025

In a system with multiple processors sharing a common bus, what is the primary role of a Bus Grant signal when sent to a processor?

• (A) It allows the processor to access memory directly without bus arbitration.

• (B) It grants the processor exclusive access to the bus for communication.

• (C) It signals the processor to disconnect from the bus for DMA access.

• (D) It instructs the processor to flush its cache before accessing the bus.

Answer: (B) It grants the processor exclusive access to the bus for communication. The arbiter gives one requester control for a transaction. A grant is neither an arbitration bypass nor a flush or disconnect order.

Q11. Bus bandwidth after halving cycle time

Suppose that a bus has 16 data lines and requires 4 cycles of 250 nsecs each to transfer data. The bandwidth of this bus would be 2 Megabytes/sec. If the cycle time of the bus was reduced to 125 nsecs and the number of cycles required for transfer stayed the same what would the bandwidth of the bus?

• (A) 1 Megabyte/sec

• (B) 4 Megabyte/sec

• (C) 8 Megabyte/sec

• (D) 2 Megabyte/sec

Answer: (B) 4 Megabyte/sec. First check: 16 bits = 2 bytes, and 4 x 125 ns = 500 ns = 500 x 10^-9 s. Therefore 2 bytes / (500 x 10^-9 s) = 4,000,000 bytes/s = 4 MB/s.

Second check: halving cycle time with width and cycle count fixed doubles the given 2 MB/s to 4 MB/s.

Cross-concept matching across DMA, cache, interrupts and the ALU

Lock cache with high-speed RAM and condition codes with ALU flags. Then separate disk DMA from printer interrupts.

Q12. Match I/O methods and hardware roles

The correct matching for the following pairs is

(A) DMA I/O (1) High speed RAM

(B) Cache (2) Disk

(C) Interrupt I/O (3) Printer

(D) Condition Code Register (4) ALU

• (A) ( A - 4 , B - 3, C - 1, D - 2 )

• (B) ( A - 2 , B - 1 , C - 3 , D - 4 )

• (C) ( A - 4 , B -3, C - 2, D- 1 )

• (D) ( A - 2, B - 3, C - 4 , D- 1 )

Answer: (B) ( A - 2 , B - 1 , C - 3 , D - 4 ). DMA suits disk blocks, cache uses fast RAM, printers interrupt, and ALU results set condition flags. Lock B - 1 and D - 4, then finish the I/O pairs.

Input Output Organisation MCQs: the short version and next step

Answer map: Q1 C, Q2 B, Q3 B, Q4 B, Q5 B, Q6 C, Q7 A, Q8 A, Q9 C, Q10 B, Q11 B, Q12 B. Reattempt missed buckets after one day, then redo the set unaided.

Identify the property, separate notification from transfer, decide who owns the bus, then attach units. Compare wider routes at GATE CS Exam Preparation Courses & Test Series. For topic-only revision, explain every wrong option aloud before opening another mixed practice set.