Writing the effective-address rule before reading the options prevents the most common confusion among immediate, indirect, register-indirect and indexed modes. First master basic mode recognition, then progress to effective-address arithmetic, bit-field sizing and a full instruction trace. For a broader mix that also covers zero-, one-, two- and three-address instruction formats, use Addressing Modes MCQs: 12 Solved COA Questions.
Addressing modes in one effective-address table
Use one notation: A is the address field or displacement, R is a register's content, M[x] is the value at memory address x, PC is the program counter, and EA is the effective address.
Mode | Where the operand comes from | EA rule | Worked value |
|---|---|---|---|
Immediate | The instruction | No data-memory EA |
|
Register | The named register | No data-memory EA |
|
Direct or absolute | Memory |
|
|
Memory indirect | Memory through a pointer |
|
|
Register indirect | Memory through a register |
|
|
Indexed or displacement | Memory at register plus offset |
|
|
PC-relative | Memory relative to |
|
|
Textbooks may separate base, indexed and displacement naming more finely. In an MCQ, calculate the address first, then choose the closest supplied label.
Immediate and register-indirect addressing MCQs
Q1. Immediate data inside the instruction
Source: ISRO 2020. Open the live solved question.
Question: "The immediate addressing mode can be used for Loading internal registers with initial values. Perform arithmetic or logical operation on data contained in instructions. Which of the following is true ?"
A. Only 1
B. Only 2
C. Both 1 and 2
D. Immediate mode refers to data in cache
Answer: C. Both 1 and 2. The instruction can carry a constant that initialises a register or participates in an arithmetic or logical operation. Immediate mode says nothing about the cache.
Q2. Address held in BX
Source: ISRO 2011. Open the live solved question.
Question: "MOV [BX], AL type of data addressing is called ?"
A. register
B. immediate
C. register indirect
D. register relative
Answer: C. register indirect. BX holds the destination address. With BX=8200, [BX] means M[8200]; AL supplies the data.
Q3. Cost of memory-indirect addressing
Source: DSSSB 2021, TGT Shift 5. Open the live solved question.
Question: "How many memory references are required to fetch an operand in indirect addressing?"
A. 1
B. 2
C. 3
D. 4
Answer: B. 2. Count after instruction fetch. For A=6000, the first reference reads M[6000]=8200, the effective address. The second reads the operand from M[8200].
Indexed, displacement and base-register MCQs
Q4. Register plus constant displacement
Source: ISRO 2017, December. Open the live solved question.
Question: "Consider the instruction LW R1, 20(R2). During execution it reads a 32-bit word from memory and stores it in 32-bit register R1. The effective address of the memory location is obtained by adding constant 20 to the contents of R2. Which option best reflects the addressing mode used for the memory operand?"
A. Immediate addressing
B. Register addressing
C. Register Indirect addressing
D. Indexed addressing
Answer: D. Indexed addressing. EA=contents(R2)+20. With R2=8000, EA=8000+20=8020. The 20 is an offset, not operand data. Pure register indirect has no offset.
Q5. Name the register-plus-constant rule
Source: UGC NET 2012, December. Open the live solved question.
Question: "In which addressing mode, the effective address of the operand is generated by adding a constant value to the contents of register?"
A. absolute mode
B. immediate mode
C. indirect mode
D. index mode
Answer: D. index mode. For register 8000 and constant 20, EA=8000+20=8020. Immediate mode is wrong because the constant forms an address instead of becoming the operand.
Q6. Modes matched to constants, pointers and loops
Source: GATE 2000. Open the live solved question.
Question: "The most appropriate matching for the following pairs is: X: Indirect addressing -> 1: Loops Y: Immediate addressing -> 2: Pointers Z: Auto-decrement addressing -> 3: Constants"
A. X-3, Y-2, Z-1
B. X-1, Y-3, Z-2
C. X-2, Y-3, Z-1
D. X-3, Y-1, Z-2
Answer: C. X-2, Y-3, Z-1. Indirect follows pointers, immediate carries constants, and auto-decrement updates a register while traversing a loop or stack.
Q7. Modes matched to arrays, relocatable code and array parameters
Source: GATE 2001. Open the live solved question.
Question: "Which is the most appropriate match for the items in the first column with the items in the second column? X. Indirect Addressing I. Array implementation Y. Indexed Addressing II. Writing relocatable code Z. Base Register Addressing III. Passing array as parameter"
A. (X, III) (Y, I) (Z, II)
B. (X, II) (Y, III) (Z, I)
C. (X, III) (Y, II) (Z, I)
D. (X, I) (Y, III) (Z, II)
Answer: A. (X, III) (Y, I) (Z, II). Passing an array uses its address, indexing selects elements, and a base register supplies the relocation base. At base 5000, width 4 and index 3, EA=5000+3x4=5012.
Follow the extra pointer in indirect addressing
Q8. What the address field contains
Source: UGC NET 2008, December. Open the live solved question.
Question: "In the indirect addressing scheme, the second part of an instruction contains:"
A. the operand in decimal form
B. the address of the location where the value of the operand is stored
C. the address of the location where the address of the operand is stored
D. the operand in an encoded form
Answer: C. the address of the location where the address of the operand is stored. The chain is instruction field 6000, M[6000]=8200, EA=8200, operand =M[8200]. Direct addressing would use EA=6000.
Common trap | Correction |
|---|---|
Immediate value versus an address | Immediate mode puts the operand in the instruction, so no data-memory EA is calculated. |
Direct versus indirect | Direct uses |
Register versus register indirect | Register gives |
Register indirect versus indexed | Register indirect uses |
Instruction boundaries and bit-field allocation MCQs
Q9. Legal program-counter value
Source: GATE 2006 and ISRO 2009. Open the live solved question.
Question: "A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?"
A. 400
B. 500
C. 600
D. 700
Answer: C. 600. Each instruction occupies 24/8=3 bytes, so legal addresses are 300+3n. The option differences are 100, 200, 300 and 400; only 300 is divisible by 3. Thus 600=300+100x3.
Q10. Split a 32-bit instruction for 256 K words
Source: UGC NET 2018, December. Open the live solved question.
Question: "A computer uses a memory unit with 256 K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code and a register code part to specify one of 64 registers and an address part. How many bits are there in the operation code, the register code part and the address part?"
A. 7,6,18
B. 6,7,18
C. 7,7,18
D. 18,7,7
Answer: A. 7,6,18. 256K=2^8x2^10=2^18, so the address needs 18 bits. 64=2^6, so the register needs 6 bits. Opcode =32-1-6-18=7 bits. Check: 1+7+6+18=32.
Q11. Split a 32-bit instruction for 512 K words
Source: UGC NET 2019, December. Open the live solved question.
Question: "A computer uses a memory unit of 512𝐾 words of 32 bits each. A binary instruction code is stored in one word of the memory. The instruction has four parts: an addressing mode field to specify one of the two-addressing mode (direct and indirect), an operation code, a register code part to specify one of the 256 registers and an address part. How many bits are there in addressing mode part, opcode part, register code part and the address part?"
A. 1,3,9,19
B. 1,4,9,18
C. 1,4,8,19
D. 1,3,8,20
Answer: C. 1,4,8,19. Two modes need log2(2)=1 bit. 256 registers need 8 bits, and 512K=2^9x2^10=2^19 words need 19 address bits. Opcode =32-1-8-19=4 bits. Check: 1+4+8+19=32.
Full instruction trace with immediate and indexed operands
Q12. Track registers and memory without skipping a line
Source: GATE 2006, Information Technology. Open the live solved question.
The memory locations 1000, 1001 and 1020 have data values 18, 1 and 16 respectively before the following program is executed.
MOVI Rs, 1 ; Move immediate
LOAD Rd, 1000(Rs) ; Load from memory
ADDI Rd, 1000 ; Add immediate
STOREI 0(Rd), 20 ; Store immediateWhich of the statements below is TRUE after the program is executed ?
A. Memory location 1000 has value 20
B. Memory location 1020 has value 20
C. Memory location 1021 has value 20
D. Memory location 1001 has value 20
Answer: D. Memory location 1001 has value 20. Trace every instruction.
Instruction | Address calculation | Register result | Memory change |
|---|---|---|---|
| Immediate operand, no EA |
| None |
|
|
| None |
| Immediate addition, no EA |
| None |
|
|
|
|
Only address 1001 is written. M[1000]=18 and M[1020]=16 remain unchanged.
Score the set, fix the weak mode, then practise
A score of 10-12 means you are ready for a timed mixed set. At 7-9, revise the EA table and redo Q4, Q8 and Q12. At 0-6, rebuild direct, indirect, register indirect and indexed rules before adding time pressure. Use these bands only to choose revision depth; they do not predict an exam score.
Redo every missed question from the effective-address table before changing topics. Use GATE Guidance by Sanchit Sir for structured Computer Architecture learning, the GATE Test Series for timed practice, and the GATE CS Exam Preparation Courses & Test Series to compare the wider preparation route.
