Memory-performance questions look alike, but their timing models change: a miss may include cache lookup, use a combined penalty, or make L2 probability conditional on L1. Performance arithmetic depends on path-weighted AMAT, bank iterations, refresh overhead and multi-level block transfers, not only cache-layout basics. Attempt each question before reading its explanation. Use GATE CS Exam Preparation Courses & Test Series for the wider route. For further practice, use the Memory Organisation & Performance module.
Timing terms and single-level cache performance
Identify each time and the miss cost.
Q1. Memory cycle time
The minimum time delay between the initiation of two independent memory operations is called
(a) Access time
(b) Cycle time
(c) Rotational time
(d) Latency time
Answer: (b) Cycle time. Access time runs from request to data availability. Cycle time separates the initiation of independent operations.
ISRO 2015. Memory Organisation & Performance module.
Q2. Average access time with an explicit cache lookup on a miss
A cache memory needs an access time of 30 ns and main memory 150 ns, what is the average access time of CPU (assume hit ratio = 80%)?
(a) 60
(b) 30
(c) 150
(d) 70
Answer: (a) 60 ns. Here Tavg = H x Tc + (1 - H) x (Tc + Tm) = 0.8 x 30 + 0.2 x (30 + 150) = 24 + 36 = 60 ns. The tempting 54 ns omits cache lookup on a miss.
ISRO Computer Science, May 2017. Use the module route above.
Q3. Cache speed gain
How much speed do we gain by using the cache when the cache is used 80% of the time? Assume the cache is 20 times faster than the main memory.
(a) 5.27
(b) 2.00
(c) 4.16
(d) 6.09
Answer: (c) 4.16. With Tc = 1, Tm = 20, time is 0.8 x 1 + 0.2 x 20 = 4.8; gain is 20/4.8 = 4.166..., approximately 4.16. It is below the ceiling 1/(1 - 0.8) = 5.
ISRO 2013. Use the module route above.
Two-level AMAT and reverse-solving miss rates
L2 hit rate is conditional after L1 miss. Weight by path probability.
Q4. Forward AMAT from two hit rates
Consider a system with two-level caches. Access times of Level 1 cache, Level 2 cache and main memory are 1 ns, 10 ns, and 500 ns, respectively. The hit rates of Level 1 and Level 2 caches are 0.8 and 0.9, respectively. What is the average access time of the system ignoring the search time within the cache?
(a) 13.0 ns
(b) 12.8 ns
(c) 12.6 ns
(d) 12.4 ns
Answer: (c) 12.6 ns. Weight paths as 0.8 x 1 + 0.2 x 0.9 x 10 + 0.2 x 0.1 x 500. This gives 0.8 + 1.8 + 10 = 12.6 ns.
GATE IT 2004; ISRO 2016. Use the module route above.
Q5. Recover both miss rates from AMAT
In a two-level cache system, the access times of \(L_1\) and \(L_2\) caches are 1 and 8 clock cycles, respectively. The miss penalty from the \(L_2\) cache to main memory is 18 clock cycles. The miss rate of \(L_1\) cache is twice that of \(L_2\). The average memory access time (AMAT) of this cache system is 2 cycles. The miss rates of \(L_1\) and \(L_2\) respectively are
(a) 0.111 and 0.056
(b) 0.056 and 0.111
(c) 0.0892 and 0.1784
(d) 0.1784 and 0.0892
Answer: (a) 0.111 and 0.056. Let L2 miss rate be x, L1 be 2x: 2 = 1 + 2x(8 + 18x), or 36x^2 + 16x - 1 = 0. The valid root is x = 1/18 = 0.0556; 2x = 1/9 = 0.1111.
GATE CS 2017, Set 2. Solution.
Interleaving and cache-line fill latency
Separate bytes, iterations, latency and transfer time.
Q6. Parallel banks and repeated iterations
A CPU has a cache with block size 64 bytes. The main memory has k banks, each bank being c bytes wide. Consecutive c − byte chunks are mapped on consecutive banks with wrap-around. All the k banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the k banks in parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes k/2 ns. The latency of one bank access is 80 ns. If c = 2 and k = 24, the latency of retrieving a cache block starting at address zero from main memory is:
(a) 92 ns
(b) 104 ns
(c) 172 ns
(d) 184 ns
Answer: (d) 184 ns. An iteration retrieves 24 x 2 = 48 bytes, so ceil(64/48) = 2. Each costs 24/2 + 80 = 92 ns; total is 2 x 92 = 184 ns.
GATE CS 2006. Solution.
Q7. Latency plus bandwidth
A cache line is 64 bytes. The main memory has latency 32 ns and bandwidth 1 GByte/s. The time required to fetch the entire cache line from the main memory is
(a) 32 ns
(b) 64 ns
(c) 96 ns
(d) 128 ns
Answer: (c) 96 ns. At 1 GByte/s, 64 bytes takes 64 ns. Add latency: 32 + 64 = 96 ns; Q6 repeats latency per iteration.
GATE IT 2006. Solution.
DRAM refresh overhead without unit mistakes
Use 1 ms: multiply count by refresh time, convert, then divide.
Q8. Thirty-two refreshes per millisecond
A dynamic RAM has a refresh cycle of 32 times per millisecond. Each refresh operation requires 100 ns, and a memory cycle requires 250 ns. What percentage of the memory's total operating time is required for refreshes?
(a) 0.64
(b) 0.96
(c) 2.00
(d) 0.32
Answer: (d) 0.32. In 1 ms, refresh takes 32 x 100 ns = 3200 ns = 0.0032 ms. Thus (0.0032/1) x 100 = 0.32%; 250 ns is irrelevant.
UGC NET CS, Paper 2, December 2015. Use the module route above. Contrast: Memory Management & Paging MCQs.
Q9. One hundred refreshes per millisecond
A dynamic RAM has a memory cycle time of 64 nsec. It has to be refreshed 100 times per msec and each refresh takes 100 nsec. What percentage of the memory cycle time is used for refreshing?
(a) 10
(b) 6.4
(c) 1
(d) .64
Answer: (c) 1. Refresh takes 100 x 100 ns = 10,000 ns per 1,000,000 ns. Therefore (10,000/1,000,000) x 100 = 1%.
GATE IT 2005. Solution.
Multi-level block transfers: one hit path and one double-miss path
Four words move per beat. L1 needs one; L2 needs four.
Q10. L2 hit after an L1 miss
A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times for L1 cache, L2 cache and main memory are 2 nanoseconds, 20 nanoseconds and 200 nanoseconds, respectively. When there is a miss in L1 cache and a hit in L2 cache, a block is transferred from L2 cache to L1 cache. What is the time taken for this transfer?
(a) 2 nanoseconds
(b) 20 nanoseconds
(c) 22 nanoseconds
(d) 88 nanoseconds
Answer: (c) 22 nanoseconds. The L1 block takes one 4-word beat. L2 plus L1 time is 20 + 2 = 22 ns.
GATE CS 2010. Solution.
Q11. Miss in both caches
A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times for L1 cache, L2 cache and main memory are 2 nanoseconds, 20 nanoseconds and 200 nanoseconds, respectively. When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?
(a) 222 nanoseconds
(b) 888 nanoseconds
(c) 902 nanoseconds
(d) 968 nanoseconds
Answer: (c) 902 nanoseconds. Main to L2 needs 16/4 = 4 beats at 200 + 20 = 220 ns, totalling 880 ns. Add 22 ns: 880 + 22 = 902 ns.
GATE CS 2010. Solution.
Locality, associativity and the compulsory-miss bound
Reuse distance counts intervening blocks; associativity controls LRU retention.
Q12. Miss ratio under a reuse-distance bound
An access sequence of cache block addresses is of length \(N\) and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by \(k\). What is the miss ratio if the access sequence is passed through a cache of associativity \(A\geq k\) exercising least-recently-used replacement policy?
(a) \(n/N\)
(b) \(1/N\)
(c) \(1/A\)
(d) \(k/n\)
Answer: (a) \(n/N\). The intended GATE interpretation treats A >= k as enough to retain a reused block, so only the first reference to each of the n distinct blocks misses and the ratio is n/N. Read literally, if k other blocks all map to the same set, the boundary case A = k can evict the earlier block; A > k makes the guarantee exact.
GATE CS 2014, Set 1. Solution.
Error log and next practice step
Family | Write first | Trap | Check |
|---|---|---|---|
One-level | Miss cost | Omitted lookup | Q3 |
Conditional | Path chances | Global rate | Branch after L1 |
Reverse |
| Swapped rates | Substitute |
Interleaving | Bytes/iteration | One iteration | Q6: |
Latency + bandwidth | Add | Omitted transfer | Q7 |
Refresh |
| Mixed units | Q8, Q9 |
Transfers | Beats x cost | One beat | Q11 = Q10 + |
LRU | Compulsory misses | Every reuse misses | Later hits |
Next try Floating Point Representation. GATE Guidance by Sanchit Sir structures COA; the GATE Test Series gives timed practice. Redo Q4, Q6, Q9 and Q11 without notes.
