Addressing modes and instruction formats are the part of Computer Organization that examiners return to every single year. The ideas are compact but easy to confuse: how the CPU computes an effective address in each mode, why relative addressing suits position-independent code, and how bits split between opcode, register and address fields in a zero, one, two or three-address instruction.
The questions that follow run from GATE 1996 to GATE 2026, with UGC NET and ISRO papers in between, and they keep circling those same few ideas. Attempt each one before reading the explanation, then follow the links into the Instruction Formats and Addressing Modes module whenever a mode still feels shaky.
Addressing modes and the effective address
Q1. In the absolute addressing mode: (GATE 2002)
(a) the operand is inside the instruction
(b) the address of the operand is inside the instruction
(c) the register containing the address of the operand is specified inside the instruction
(d) the location of the operand is implicit
Answer: (b). In absolute addressing, also called direct addressing, the address field of the instruction holds the memory address of the operand, and the CPU fetches the operand from there. Option (a) describes immediate addressing, where the value itself sits in the instruction, and (c) describes register-indirect addressing (see the full solution).
Q2. In which addressing mode is the effective address of the operand generated by adding a constant value to the contents of a register? (UGC NET 2012)
(a) absolute mode
(b) immediate mode
(c) indirect mode
(d) index mode
Answer: (d) index mode. In indexed addressing the effective address is a constant displacement added to the contents of an index register, that is, EA = displacement plus the index register. Advance that register by one element width and the same instruction reaches the next array element, which is why compilers reach for this mode inside loops. The distractors fail on the addition: (a) puts the address itself in the instruction and (c) puts the address of an address there, and neither adds a register to anything. More practice on this pattern sits in the Instruction Formats and Addressing Modes module.
Q3. In the indirect addressing scheme, the second part of an instruction contains: (UGC NET 2008)
(a) the operand in decimal form
(b) the address of the location where the value of the operand is stored
(c) the address of the location where the address of the operand is stored
(d) the operand in an encoded form
Answer: (c). Indirect addressing stores a pointer, not the operand and not even the operand's address directly. The address field points to a memory location that itself holds the effective address, so the CPU needs one extra memory access to reach the operand. Watch the wording that separates (b) from (c); it is the whole trick.
Q4. The most appropriate matching for the pairs X: Indirect addressing, Y: Immediate addressing, Z: Auto-decrement addressing with 1: Loops, 2: Pointers, 3: Constants is (GATE 2000)
(a) X-3, Y-2, Z-1
(b) X-1, Y-3, Z-2
(c) X-2, Y-3, Z-1
(d) X-3, Y-1, Z-2
Answer: (c) X-2, Y-3, Z-1. Indirect addressing works through a stored address, so it maps to pointers. Immediate addressing embeds the value, so it maps to constants. Auto-decrement steps a register automatically each access, which is what loops over a data structure need (see the full solution).
Relative, indexed and auto-increment modes
Q5. Relative mode of addressing is most relevant to writing (GATE 1996)
(a) co-routines
(b) position-independent code
(c) shareable code
(d) interrupt handlers
Answer: (b) position-independent code. In relative addressing the effective address is the program counter plus an offset, so the code refers to targets by distance rather than by fixed address. Move the whole block anywhere in memory and every offset still resolves correctly, which is precisely what position-independent code requires (see the full solution).
Q6. Which statement about relative addressing mode is FALSE? (GATE 2006)
(a) It enables reduced instruction size
(b) It allows indexing of array elements with the same instruction
(c) It enables easy relocation of data
(d) It enables faster address calculations than absolute addressing
Answer: (d). The clean discriminator is hardware cost: relative addressing must add the program counter to a displacement before it can touch memory, so its address calculation is strictly slower than absolute addressing, which uses the address exactly as given. That makes (d) the false statement. The other three are the standard properties of a base-plus-displacement mode: an offset needs far fewer bits than a full address, so the instruction shrinks (a); the base-plus-displacement form is the same arithmetic that walks consecutive array elements (b); and code that names targets by distance relocates without rewriting a single address (c) (see the full solution).
Q7. A three-word instruction ADD A[R0], @B keeps the opcode and the mode bits in its first word, the address A in the second and the address B in the third. The destination A[R0] uses indexed addressing with R0 as the index register, the source @B uses indirect addressing, and the sum is written back to the destination. How many memory accesses happen during the execute phase, excluding the three instruction-word fetches? (GATE 2005)
(a) 3
(b) 4
(c) 5
(d) 6
Answer: (b) 4. A and B arrive with the instruction, so neither costs a separate read. Reading the indexed operand at A plus R0 is one access. The indirect source needs one access to read the effective address out of B and another to read the operand it points at, which is two. Writing the sum back to A plus R0 is the fourth. Add the three instruction-word fetches and a question asking for the total instead answers seven (see the full solution).
Q8. Which of the following is true of the auto-increment addressing mode? I. It is useful in creating self-relocating code. II. It requires an additional ALU for effective-address calculation. III. The amount of increment depends on the size of the data item accessed. (ISRO 2009, GATE 2008)
(a) I only
(b) II only
(c) III only
(d) II and III only
Answer: (c) III only. Statement III is the real property: the register advances by one element width, so a 4-byte item increments the pointer by 4. Statement I is false because self-relocation relies on relative addressing, and II is false because the standard ALU handles the increment with no extra hardware.
Instruction formats: zero, one, two and three-address
Q9. Computers can have instruction formats with (UGC NET 2013)
(a) only two-address and three-address instructions
(b) only one-address and two-address instructions
(c) only one-address, two-address and three-address instructions
(d) zero-address, one-address, two-address and three-address instructions
Answer: (d). All four formats exist. Zero-address instructions are stack-based (operands are implicit on the stack), one-address instructions name a single operand and use an implied accumulator, and two and three-address instructions name their operands explicitly. The number of addresses is just how many operands the format spells out.
Q10. A processor P has a load-store instruction set architecture, and the first operand of any instruction is the destination. Which sequence implements Z = X + Y, where X, Y, Z are memory operands and R0, R1, R2 are registers? (GATE 2026)
(a) ADD Z, X, Y
(b) LOAD R0, X; ADD Z, R0, Y
(c) ADD R0, X, Y; STORE Z, R0
(d) LOAD R0, X; LOAD R1, Y; ADD R2, R0, R1; STORE Z, R2
Answer: (d). In a load-store architecture arithmetic runs only on registers, so memory operands must be loaded first. Load X into R0 and Y into R1, add them into R2, then store R2 back to Z. The other sequences try to feed memory operands straight into ADD, which the architecture does not allow (see the full solution).
Instruction encoding: opcode, register and immediate fields
Q11. A processor has 64 general-purpose registers and 50 distinct instruction types, and an instruction is encoded in 32 bits. For an instruction like ADD R1, #25, what is the maximum number of bits available for the immediate operand? (GATE 2025)
(a) 16
(b) 20
(c) 22
(d) 24
Answer: (b) 20. The opcode must separate 50 instruction types, so it needs ceil(log2 50) = 6 bits, and naming one of 64 registers needs exactly log2 64 = 6 bits. That leaves 32 minus 6 minus 6 = 20 bits for the immediate. The trap is how many register fields to charge: ADD R1, #25 names a single register, so only one 6-bit field is subtracted, while a two-register form would leave 14 (see the full solution).
Q12. A computer uses a memory unit of 256K words of 32 bits each. An instruction has an indirect bit, an opcode, a register field to specify one of 64 registers, and an address field. How many bits are in the opcode, the register field and the address field? (UGC NET 2018)
(a) 7, 6, 18
(b) 6, 7, 18
(c) 7, 7, 18
(d) 18, 7, 7
Answer: (a) 7, 6, 18. The address field needs log2(256K) = log2(262144) = 18 bits. The register field needs log2(64) = 6 bits. The indirect bit takes 1 bit. That leaves 32 minus 18 minus 6 minus 1 = 7 bits for the opcode.
How this topic is examined
Papers test this topic along four lines. First, mode definitions and effective-address reasoning, where the whole question turns on one clause of wording (Q1 to Q4). Second, the relative, indexed and auto-increment family, usually with a memory-access count attached (Q5 to Q8). Third, the zero to three-address taxonomy and what a load-store architecture refuses to do (Q9 to Q10). Fourth, bit-budget arithmetic on a fixed instruction word (Q11 to Q12). If you missed more than two, the gap is almost always a mode definition you half-remember rather than a lack of practice.
Rebuild the theory through the Instruction Formats and Addressing Modes module before your next mock. Once modes are solid, the natural next stop is how instructions actually flow through the datapath, which is where pipelining in computer architecture picks up. GATE aspirants get the full Computer Organization sequence inside GATE Guidance by Sanchit Sir, and you can place the subject in the wider syllabus from the GATE CS Exam category. Solve, review the ones you missed, and return a week later; the second pass is where the marks lock in.
