You may know that 1 KB = 1024 bytes yet mix up address and data lines, divide chip capacities without matching widths, or trace a cache before finding its set. Twelve previous-year questions turn those three slips into four fixed methods: a powers-of-two ladder, a depth-times-width chip rule, a set index computed before any trace, and an AMAT convention written down before substituting. Review MCQ, MSQ or NAT? GATE Question Types Explained for response formats, Cache Memory: Mapping and Hit Ratio for theory, and GATE Guidance by Sanchit Sir for a structured full-subject route.
1. Build the unit ladder before doing memory arithmetic
Write the time ladder: 1 second = 10^0 s, 1 millisecond = 10^-3 s, 1 microsecond = 10^-6 s, 1 nanosecond = 10^-9 s, and 1 picosecond = 10^-12 s. Largest to smallest: second, millisecond, microsecond, nanosecond, picosecond. Memory Hierarchy and Virtual Memory Explained places cache in context. GATE CS Exam Preparation offers broader practice.
Q1. Order the access-time units
Source: UGC NET, Paper I, June 2025. Attempt it first.
Which of the following is the correct sequence of largest to smallest unit of Memory access time?
A. Millisecond
B. Picosecond
C. Nanosecond
D. Microsecond
E. Second
(a)
E, D, C, A, B(b)
E, A, B, C, D(c)
E, A, D, C, B(d)
E, C, D, A, B
Answer: (c) E, A, D, C, B. The powers are E = 10^0, A = 10^-3, D = 10^-6, C = 10^-9, and B = 10^-12 seconds. Ordering from the least negative exponent to the most negative gives E, A, D, C, B. Check the solved page.
With n address lines, a memory has 2^n selectable locations. With m data lines, each location holds or transfers m bits, so capacity is 2^n x m bits.
Q2. Read a memory declaration correctly
Source: UGC NET, Computer Science, December 2022. Attempt it first.
The memory size for n address lines and m data lines is given by
(a)
2^m x n(b)
m x n^2(c)
2^n x m(d)
n x m^2
Answer: (c) 2^n x m. For n = 14 and m = 16, there are 2^14 = 16,384 words, each 16 bits wide. Capacity is 2^14 x 16 = 262,144 bits = 32 KiB; see the solved page.
2. Address lines, data lines, and word-addressable memory
These questions use the binary convention: 1 MB = 2^20 bytes and 1 GB = 2^30 bytes. For word addressing, convert to bytes, divide by bytes per word, then take log2 of the word count.
Q3. Separate word count from word width
Source: UGC NET, Computer Science, June 2019. Attempt it first.
How many address lines and data lines are required to provide a memory capacity of 16K × 16?
(a)
10,4(b)
16,16(c)
14,16(d)
4,16
Answer: (c) 14,16. 16K = 16,384 = 2^14 selectable words, so 14 address lines are required. Each word is 16 bits wide, so 16 data lines are required, in the order asked; verify it on the solved page.
Q4. Count word addresses, not bytes
Source: UPPSC Polytechnic Lecturer, Computer Science, 2018. Attempt it first.
A computer has 128 MB memory. Each word in this computer is of 8 bytes. How many bits are required to address any single word in the memory?
(a)
27(b)
24(c)
23(d)
25
Answer: (b) 24. 128 MB = 2^7 x 2^20 = 2^27 bytes; dividing by 8 bytes = 2^3 bytes per word gives 2^24 words. Selecting one word needs 24 address bits, as shown on the solved page.
Q5. Size a word-addressed bus
Source: UGC NET, Computer Science, June 2019. Attempt it first.
A processor can support a maximum memory of 4 GB where memory is word addressable and a word is 2 bytes. What will be the size of the address bus of the processor?
(a)
At least 28 bits(b)
At least 2 bytes(c)
At least 31 bits(d)
Minimum 4 bytes
Answer: (c) At least 31 bits. 4 GB = 2^32 bytes; dividing by a 2-byte word gives 2^31 addressable words. The bus therefore needs at least 31 bits, not bytes; open the solved page.
3. Solve RAM-chip configurations by depth and width separately
Use chip count = depth ratio x width ratio, and match units before dividing. A total-capacity division is a useful second check.
Q6. Find address lines for an array
Source: Indian Space Research Organization, Computer Science, 2014. Attempt it first.
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a 4 x 6 array, where each chip is 8K x 4 bits ?
(a)
13(b)
15(c)
16(d)
17
Answer: (d) 17. There are 4 x 6 = 24 chips, so capacity is 24 x 8K x 4 bits = 786,432 bits = 98,304 bytes. Since 2^16 = 65,536 < 98,304 <= 131,072 = 2^17, the minimum is 17 address lines; see the solved page.
Q7. Expand both depth and width
Source: Indian Space Research Organization, Computer Science, May 2017. Attempt it first.
How many 128 × 8 bit RAMs are required to design 32 K × 32 bit RAM?
(a)
512(b)
1024(c)
128(d)
32
Answer: (b) 1024. The depth ratio is 32K / 128 = 32,768 / 128 = 256, and the width ratio is 32 / 8 = 4, giving 256 x 4 = 1,024 chips. The total-bit check, (32K x 32) / (128 x 8), also gives 1,024; inspect the solved page.
Q8. Preserve the byte-to-bit factor
Source: Indian Space Research Organization, Computer Science, 2015. Attempt it first.
How many 32K × 1 RAM chips are needed to provide a memory capacity of 256 Kbytes?
(a)
8(b)
128(c)
32(d)
64
Answer: (d) 64. 256 Kbytes = 256K x 8 bits, while one chip supplies 32K x 1 bit. The ratio is (256K x 8) / (32K x 1) = 8 x 8 = 64; the distractor 8 drops the byte-to-bit conversion. Continue on the solved page.
4. Recognise mapping types and calculate cache lines
Direct mapping gives each memory block one possible cache line. Fully associative mapping permits any line, while k-way set-associative mapping selects one set and permits any of its k ways.
Q9. Identify valid mapping schemes
Source: DSSSB, Computer Science, 2018. Attempt it first.
Identify the valid cache organization techniques:
(i) Direct
(ii) Associative
(iii) Set-associative
(a)
(i) and (ii) only(b)
(ii) and (iii) only(c)
(i) and (iii) only(d)
(i), (ii) and (iii)
Answer: (d) (i), (ii) and (iii). All three are valid cache block-placement organizations. They differ in the candidate lines available to a memory block, not in whether the cache uses blocks and tags; see the solved page.
Q10. Divide cache capacity by block size
Source: CDAC CCAT, 2025. Attempt it first.
A direct-mapped cache has a total size of 1 KB with a block size of 16 bytes. The number of cache lines is:
(a)
32(b)
64(c)
128(d)
256
Answer: (b) 64. Under the question's convention, 1 KB = 1024 bytes, so 1024 / 16 = 64 cache lines. Those lines need log2(64) = 6 index bits, although only the line count is asked; verify it on the solved page.
5. Trace a 2-way set-associative cache without guessing
Four total blocks in a 2-way cache give 4 / 2 = 2 sets, from sets = blocks / associativity. With block addresses supplied, use set = block address mod 2; 8, 12 and 0 are all even, so all three compete for the same two ways in set 0, leaving set 1 untouched. An odd address such as 9 would have landed in set 1 and cost nothing, which is why the set index is worth computing before any replacement rule is applied.
Q11. Follow LRU after every access
Source: BEL, Computer Science, 2007. Attempt it first.
Consider a small 2-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently (LRU) scheme. The number of cache misses for the following sequence of block addresses is 8,12,0,12,8
(a)
2(b)
3(c)
4(d)
5
Answer: (c) 4. The trace is 8 M, 12 M, 0 M, 12 H, 8 M, which gives four misses. The hit on 12 refreshes it, so the final miss evicts 0 rather than 12; the solved page steps through the same sequence.
6. Compute AMAT with the miss-penalty convention stated
First calculate miss rate = 1 - hit ratio. Here, the stated miss penalty is the extra cost after the hit lookup, so use AMAT = hit time + miss rate x miss penalty.
Q12. Include the lookup time
Source: CDAC CCAT, 2025. Attempt it first.
In a cache, if the hit ratio is 0.9, hit time is 2 ns and miss penalty is 100 ns, the average memory access time is:
(a)
10 ns(b)
12 ns(c)
20 ns(d)
100 ns
Answer: (b) 12 ns. The miss rate is 1 - 0.9 = 0.1, so AMAT = 2 ns + 0.1 x 100 ns = 12 ns. Ten nanoseconds omits the lookup time; if another problem defines the complete miss time instead, follow that wording. See the solved page.
7. Five checks for units, memory, cache, and AMAT
Before solving, run five checks:
Convert every unit into powers of two first:
1 KB = 2^10,1 MB = 2^20and1 GB = 2^30bytes.Count addressable locations, not bytes, whenever the memory is word addressable: divide the byte total by bytes per word, then take
log2of the word count.Keep depth and width separate:
chips = depth ratio x width ratio, never a single division across mismatched units such as bits over bytes.Fix the cache geometry before tracing anything:
lines = cache size / block size, thensets = lines / associativity.Write the AMAT convention down before substituting:
hit time + miss rate x miss penaltywhen the penalty is the extra cost after a failed lookup, andhit rate x hit time + miss rate x miss timewhen the question defines the complete miss time instead.
Now redo Q3, Q7, Q11, and Q12 without looking. Together they test address and data lines, chip count, LRU tracing, and average access time. To take Computer Organization end to end rather than question by question, continue with GATE Guidance by Sanchit Sir.
Say the procedure before using the calculator, then write every power of two.
